cmos电荷泵锁相环的设计及相位噪声的研究微电子学与固体电子学专业论文.docxVIP

Design Design of a CMOS Charge--Pump PLL and Investigation of the Phase Noise Abstract With the development‘of the integrated circuit technology，the PLL(Phase Locked Loop)obtains more and more attention．CPPLLs(Charge·Pump PLL) become the mainstream and play an important role in VLSI and SoC(System on Chip)because of the merit of smaller phase difference and bigger capture range． This thesis designed a CPPLL which was based on CMOS technology and adopted top·down method．Firstly,the VHDL-AMS behavioral modeling of the close—loop system was desi gned based on the fundamental of CPPLL and the characteristic of VHDL-AMS language．Then，phase frequency detector，charge pump，loop filter，voltage controlled oscillator，divider and the clock distribution circuit were designed under the guidance of the behavioral model and the specification of the application system．Phase noise and jitter were analysed and simulated on the model．Finally，the layout was designed and taped out． The D／A converter including the CPPLL which was designed by this thesis has been fabricated in MPW based on the CMOS O．35um 2P3M technology and passed the preliminary tests．The actual PLL circuit supports frequency division of 4-32， and outputs clock signals of different frequency．The power supply is 3．3钐 adj ustable frequency range is 96～400MHz．The power dissipation is less than 45mW．and the noise iS less than 1 00dBc／Hz． Keywords：charge-pump phase locked loop，VHDL-AMS，behavioral modeling， phase noise，j itter 插图清单图1．1电荷泵锁相环的结构 插图清单 图1．1电荷泵锁相环的结构 2 图2．1电荷泵锁相环的结构 5 图2．2二阶PLL的动态和静态稳定范围 7 图2．3锁相环锁定过程 ．．7 图2—4锁相环能量谱 ．8 图2．5具有抖动的时钟信号 ．．8 图2-6鉴相器的示意图 1 3 图2—7鉴频鉴相器框图及其状态转换 13 图2—8基本的电荷泵结构 ．．14 图2-9三阶无源低通滤波器 ．．15 图2．1 0压控振荡器 。l 7 图2．1l PLL行为模型的仿真 ．．20 图3．1 DAC系统结构图 22 图3．2鉴相“死区” 24 图3．3鉴频鉴相器 25 图3．4电荷泵电荷泄漏 26 图3．5电流失配的影响 26 图3．6电荷共享效应 27 图3．7采用自举电路消除电荷共享 ．．27 图3—8电荷泵电路 28 图3-9滤波器 29 图3．10三阶滤波器的频率特性 ．．30 图3．1 1系统开环幅频特性 ．33 图3．1 2负反馈系统 ．．34 图3．1 3 N级环形振荡器 34 图3．1 4六级环形振荡器 ．35 图3．15本设计的VCO差动振荡单元 ．．36 图3．1 6整形电路 38 图3．17