基于多扫描链的集成电路内建自测试方法研究-计算机应用技术专业论文.docxVIP

The The Study on Built-in Self-test(BIST)For Integrated Circuits Based—OU Multiple Scan Chains Abstract As the integration density of the integrated circuits increase，more and more functionality can be packed into a chip．which is called sytem on chip(SoC)．This requires a significant increase in test generation difficulty and results in large test data volumes．Application of these test data requires sophisticated，high speed automatic test equipment(ATE)and Iong test time．So test cOSt is very high， typically is order of several Dollars per minute．Besides，the number of pin counts grows at a slower pace than silicon density，limiting the increase in test application bandwidth and lengthening the test application time．Furthermore，the semiconductor technology of products under test is ahead of the technology of ATE． So it may not provide at-speed testing． Built-in Self-test(BIST)offers蛆attractive alternative to conventional external testing methods．By moving test generation，application and test response into the chip itself,BIST eliminates the need for expensive ATE，reduces the test cost and cart provide at-speed testing．The thesis addresses several issues related to BIST for multiple SCan chains． Initially，several basic concepts and methods about design for testability(DFT) and SoC test techniques are introduced． Secondly，logic BIST iS extensively studied especially test pattern generation techniques．Exhaustive testing，pseudoexhaustive testing，pseudorandom testing， weighted testing and‘‘store and generate”testing are described in detail． Thirdly，an improved design algorithm of phase shifter is proposed．Phase shifter Can overcome the data dependency among scan chains during pseudorandom testing and plays an important role in the improvement of fault coverage for circuits under test(CUT)．On the base of previous phase shifter algorithm，the proposed algorithm selects xor taps by the way of an added pseudorandom sequences generation function．The experiment results sh