51单片机与fpga进行串行通信.docxVIP

51单片机与fpga进行串行通信，并显示到LCD上。下面给出串口通信USart部分程序： 1.FPGA程序： Module1（协议部分）： Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity tx is port( din:in std_logic_vector(7 downto 0); sout:out std_logic; clk:in std_logic; len_r:out std_Logic_vector(3 downto 0); txclk:in std_logic ); end tx; architecture Behavioral of tx is type s is(start,shift,stop,delay1,delay2); --type s is(start1,shift1,stop1,delay1,start2,shift2,stop2,delay2,start3,shift3,stop3,delay3,start4,shift4,stop4,delay4); signal state:s:=start; signal txcnt_r,len: std_logic_vector(3 downto 0); signal sout1: std_logic; signal thr:std_logic_vector(7 downto 0); signal clk1:std_logic; begin process(txclk) begin if txclk=1 and txclkevent then thr=din; end if; end process; process(txclk) variable tsr:std_logic_vector(7 downto 0); variable count:integer range 0 to 480:=0; variable count1:integer range 0 to 4800:=0; begin if txclk=1 and txclkevent then case state is when start= tsr:=thr; sout1=0; --传输起始位 txcnt_r=(others=0); --传输数据位数计数清0 state=shift; when shift= sout1=tsr(0); --数据位 传输第1位数据 tsr(6 downto 0):=tsr(7 downto 1);--填充数据 tsr(7):=0; txcnt_r=txcnt_r+1; if (txcnt_r=7) then state=stop; end if; when stop= sout1=1; state=delay1; when delay1= if count120 then count:=count+1; else count:=0; if len7 then state=start; len=len+1; else state=delay2; end if; end if; when delay2= if count12400 then count1:=count1+1; else count1:=0; len=0000; state=start; end if; end case; sout=sout1; len_r=len; end if; end process; process(clk) variable