雷达信号处理在FPGA中的IP核设计与实现-信号与信息处理专业毕业论文.docxVIP

摘 摘 要 随着雷达信号处理技术的不断发展，通用化、系统化、模块化的设计标准日 益受到人们的重视，而FPGA和可复用IP核技术的发展使之成为可能。文中从三 个方面进行口内核的开发，一是采用硬件描述语言实现雷达信号处理D核设计； 二是在SOPC设计思想的指导下，结合FPGA中提供的嵌入式处理器PowerPC， 实现小型实时信号处理单元的设计；三是利用Xilinx公司推出的System Generator 工具集，实现DDS模块设计。其中重点是对雷达信号处理口核的设计。 结合脉冲压缩多普勒雷达信号处理流程，文中主要对自适应波束形成、数字 下变频和脉冲压缩三种雷达信号处理算法进行口核设计。自适应波束形成模块采 用浮点脉动阵结构实现，该结构从两个方面进行设计，一方面是自定义浮点格式 及该格式下的浮点运算单元的设计；另一方面是对现有脉动阵结构的优化改进， 并在硬件上进行了实现。 结合项目需求，文中采用低通滤波法设计了数字下变频模块，提出了采用 RAM资源设计的滤波器实现方法；并分别在时域和频域对脉冲压缩算法进行了 仿真和实现。 关键字：脉动阵 自适应波束形成脉冲压缩数字下变频PowerPC IP核 AbstractWith Abstract With increasing development of radar signal processing technology,it is becoming very important to attach the significance tO universal，systematic and modular design standards，and a possibility with the development of FPGA and reusable IP core technique．IP core development is presented in three aspects．First, radar signal processing IP COre is realized by using the hardware descriptive language； and then，based on the SOPC design idea and combined with也e embedded proccesor PowerPC provided by FPGA，integrated real-time signal processing equipment is achieved；finally,the System Generator tools afforded by Xilinx company contributes to a rather convenient system design．The emphasis of this paper is the design of radar signal processing IP cores． Combined with the flow of signal processing of the pulse compression doppler radar,this paper design and implement algorithms for adaptive beamforming，digital down conversion and pulse compression．The adaptive beamforming modular is designed by using float—point systolic array structure realized in two parts：one is the achievement of the custom floating-point format and the floating-point algorithm unit； the other is the improvement on the existing systolic array structure with the implementation on hardware． Combined with the project-specific requirement，digital down conversion module mainly contains the low-pass implementation，and a relatively novel method is raised in this paper for filter realization．The simu