HFSS差分过孔的建模仿真设计.pptVIP

Differential vias simulation 2012-9-12 As data communication speeds increase beyonds 3Gbps, signal integrity becomes crucial for successful data transmission. Board designers try to eliminate every impedance mismatch along the high-speed signal path, because those discontinuities generate jitter and decrease the data eye opening-not only reducing the maximum possible distance of data transmission, but also minimizing the margin to common jitter specification The via and antipad sizes strongly determine the vias electrical characteristics. Nonfunctional pads help secure the vias in a stack up, but are not visible in the artwork and can be removed on high-speed nets. * Background The parasitic capacitance The parasitic inductance D1: The Pad Diameter D2: The Anti_pad Diameter H: The height of via D: The diameter of the via Via Model Board: Size=7mm*10mm Thickness=1.13mm DK=4.6 Df=0.02 Ground: Thickness=0.05mm Trace: Width=0.5mm Thickness=0.07mm 1. introduction 4 layer PCB with vias 4 vias connected to ground plane near the signal via Differential Signal trace Reference ground plane Signal vias 2. HFSS Model Provide the nearest signal return path or the minimal inductance return path area 3. HFSS Setting condition 1 Solution Type: Driven Terminal 2 Port define: Lumped port Excitations 3 Radiation Boundary: In order to investigate how the via effect the signal integrity on PCB. R_antipad, R_via and R_pad are taken into account D_antipad: 0.5, 0.7, 0.9mm D_via: 0.3, 0.5, 0.7mm D_pad: 0.5, 0.7, 0.9mm How to create the 3D model, pls refer to the HFSS model for details R_antipad=0.55mm, R_pad=0.45mm R_via=0.15mm, 0.25mm, 0.35mm 4.1 TDR VS R_via The smaller R_via, the better TDR continuity R_antipad=0.55mm, R_pad=0.45mm R_via=0.15mm, 0.25mm, 0.35mm 4.2 Sdd11/Sdd21 VS R_via The smaller R_via, the better insertion loss and smaller reflection R_antipad=0.45mm, R_via=0.15mm