Moore型和Mealy型状态机实例对比.docVIP

下图为某一状态机对应的状态图，试用VHDL语言描述这一状态机。（18分） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FSM1 IS PORT ( clk,reset,in1 : IN STD_LOGIC; out1 : OUT STD_LOGIC_VECTOR(3 downto 0)); END ; ARCHITECTURE bhv OF FSM1 IS TYPE state_type IS (s0, s1, s2, s3); SIGNAL current_state,next_state: state_type; BEGIN REG:PROCESS(clk,reset) BEGIN IF reset =1 THEN current_state = s0; ELSIF clk=1 AND clkEVENT THEN current_state =next_state; END IF; END PROCESS; COM1: PROCESS (current_state,in1) BEGIN case current_state is WHEN s0 = IF in1=1THEN next_state=s1;ELSE next_state=s0;END IF; WHEN s1 = IF in1=0THEN next_state=s2;ELSE next_state=s1;END IF; WHEN s2 = IF in1=1THEN next_state=s3;ELSE next_state=s2;END IF; WHEN s3 = IF in1=0THEN next_state=s0;ELSE next_state=s3;END IF; end case; END PROCESS; COM2:PROCESS(current_state) BEGIN case current_state is WHEN s0 = out1=0000; WHEN s1 = out1=1001; WHEN s2 = out1=1100; WHEN s3 = out1=1111; end case; END PROCESS; end bhv; 上面的是Moore型的， 下面的为Mealy型。 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY YH ISPORT(CLK,RST,INPUTS:IN STD_LOGIC; OUTPUTS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE ONE OF YH ISTYPE STATES IS (S0,S1,S2,S3);SIGNAL PST:STATES; BEGINREGCOM:PROCESS(CLK,RST,PST,INPUTS) BEGINIF RST=1 THEN PST=S0;ELSIF RISING_EDGE(CLK) THENCASE PST ISWHEN S0= PST=S1;WHEN S1= PST=S2;WHEN S2= PST=S3;WHEN S3= PST=S0;WHEN OTHERS = PST=S0;END CASE;END IF;END PROCESS;COM:PROCESS(PST) BEGINCASE PST ISWHEN S0= IF INPUTS=1 THEN OUTPUTS=1001 ;ELSE OUTPUTS=0000; END IF;WHEN S1= IF INPUTS=0 THEN OUTPUTS=1100 ;ELSE OUTPUTS=1001; END IF;WHEN S2= IF INPUTS=1 THEN OUTPUTS=1111 ;ELSE OUTPUTS=1100; END IF;WHEN S3= IF INPUTS=0 THEN OUTPUTS=0000 ;ELSE OUTPUTS=1111; END IF;WHEN OTHERS = OUTPUTS=0000 ;END CASE;END PROCESS;END;