VHDL与数字电路的问题.pptVIP

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity top is Port( clk : in std_logic; spkout : out std_logic); End top; Architecture a1 of top is component tone Port( index : in integer range 0 to 16; tone : out integer range 0 to 16#7FF#); end component; component speaker Port( clk : in std_logic; Freq_in : in integer range 0 to 16#7FF#; speaker : out std_logic); end component; signal index1 : integer range 0 to 16; signal tone2 : integer range 0 to 16#7FF#; signal ck4: std_logic; begin process(clk) variable q : std_logic_vector(17 downto 0); Begi