应用直接数位频率合成器架构数位调变器.pdf

應用直接數位頻率合成器架構數位調變器 學生鄭恒杉: 指導教授:李鎮宜博士 國立交通大學電機資訊學院 電子與光電學程﹙研究所﹚碩士班 摘 要 本論文嚐試著以直接數位頻率合成器實現㆒個可做FSK,DFSK,BPSK及 QPSK 等不同形式調變之數位調變器, 而此數位調變器則是架構在直接數位頻率合成器, 論文㆗亦討論正弦相位輸入及輸出位元數對正弦輸出特性的影響 ,進而利用兩段直 線作為正弦值的起始猜測值及 ROM作為補償值逼近正弦值在可接受的, SFDR ㆘ 採用分割ROM補償值來降低 ROM的大小。 ROM 表被分為粗細兩個表,粗表含有 384位元細表含有, 192位元,共用到ROM 表大小為576位元, 在合成頻率㆗模擬結, 果最差的 SFDR可達 61dBc,相關控制電路只用到加法器,不需減法及乘法器,與相同 規格的直接數位頻率合成器比較所用到的, ROM 表大小及所需控制電路皆比較小, 只是需要稍微犧牲 SFDR 特性。本文同時利用所提出的直接數位頻率合成器實現 ㆒個可做FSK,DFSK,BPSK及 QPSK 等不同形式具正餘弦調變輸出之數位調變器, 最後使用 Synplify Pro合成 verilog 碼, 並以Altera EPK100ARC240-1作為數位調變 器功能的驗證 用到, 238邏輯單元(4%)及 1152記憶位元 (2%)IC資源。 I Application Of Direct Digital Frequency Synthesizer In Digital Modulator Student : Hen-Shan Cheng Advisor : Dr. Chen-Yi Lee Degree Program of Electrical Engineering Computer Science National Chiao Tung University Abstract In this thesis, we propose a digital modulator with FSK, DFSK, BPSK and QPSK function by using direct digital frequency synthesizer (DDFS). For DDFS, the spur item were caused by finite output word length, phase truncation and sine/cosine mapping function (SCMF) are also presented. The initial guess and error correct ROM table are used to approximate the sine function, Initial guesses techniques using 2-segment line approximation. In order to reduce the ROM size, the ROM memory was partitioned into two ROM blocks. Coarse ROM (384 bits) and fine ROM (192 bits) were explored. The total size of ROM table is 576 bits. Only adder circuits were required in the additional circuits. No subtractor and multiplier were needed. Simulation shows th