中科院研究生院课程VLSI测试与可测试性设计(精).pptVIP

EE141 EE141 Chapter 3 About the Chapter Circuit simulation models Logic simulation techniques Fault simulation techniques Logic and Fault Simulation Introduction Simulation models Logic simulation Fault simulation Concluding remarks Logic Simulation Predict the behavior of a design prior to its physical realization Design verification Fault Simulation Predicts the behavior of faulty circuits As a consequence of inevitable fabrication process imperfections An important tool for test and diagnosis Estimate fault coverage Fault simulator Test compaction Fault diagnosis Logic and Fault Simulation Introduction Simulation models Logic simulation Fault simulation Concluding remarks Gate-Level Network The interconnections of logic gates Sequential Circuits The outputs depend on both the current and past input values A Positive Edge-Triggered D-FF Logic Symbols The most commonly used are 0, 1, u and Z 1 and 0 true and false of the two-value Boolean algebra u Unknown logic state (maybe 1 or 0) Z High-impedance state Not connected to Vdd or ground Ternary Logic Three logic symbols: 0, 1, and u Information Loss of Ternary Logic Simulation based on ternary logic is pessimistic A signal may be reported as unknown when its value can be uniquely determined as 0 or 1 High-Impedance State Z Tri-state gates permit several gates to time-share a common wire, called bus A signal is in high-impedance state if it is connected to neither Vdd nor ground Logic Element Evaluation Methods Choice of evaluation technique depends on Considered logic symbols Types and models of logic elements Commonly used approaches Truth table based Input scanning Input counting Parallel gate evaluation Truth Table Based Gate Evaluation The most straightforward and easy to implement For binary logic, 2n entries for n-input logic element May use the input value as table index Table size increases exponentially with the number of inputs Could be inefficient for multi-valued logic A k-symbol logic system requires a