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unique id: 086465 Documentum\SMIC-IP(Aug2001)(Scn).ppt Mechanism: Si3N4 + 6H2O -------- 3SiO2 + 4NH3 (H3PO4 as catalyst) ER A/min Si Conc. (ppm) Particle (#/ml,@0.2um) SiN SiO2 Particle Nitride Remove When the Silicon content is very high, oxide etch rate decreases. Silicon may even re-deposit on wafer and trap some H3PO4. If this Phos is implanted/driven into the wafer, it will give extra “n” type which may lead to leaky Field Oxide and poor GOI. In order to stabilize the etch loss of oxide, for the 2 H3PO4 tank process time, Tank 1 time is set to remove all the Nitride while Tank 2 takes care of the overetch. As a result, the Tank 2 oxide etchrate is more stable which leads to better oxide remains control. Oxynitride/oxide AA SiN 100A Pad Oxide HF dip AA SiN 100A Pad Oxide HPO 1 100A Pad Oxide HPO 2 AA SiN Strip Process for CM71DRAM Pad Oxide Remained HPO lifetime dependent! (Recipe NLH240AHPO2550ASC1M) SPM(Sulfuric Peroxide Mixture) 98%H2SO4 : 30% H2O2 = 5 : 1, 125C Caro’s acid / SPM / Piranha Function: Photo-resist stripping Organic contamination removal Mechanism: H2SO4 + H2O2 ? HO-(SO2)-O-OH H2SO5+ H2O HO-(SO2)-O-OH + -(CH2)n ? CO2 + H2O Use hot QDR (Quick Dump Rinse) with mega-sonic to rinse off viscous H2SO4 on wafers Recipe for PR Strip NDH10APRRMM: DHF(100:1) 15” + SPM 5’+SPM5’+HQDR(with Mega) NPRRM: SPM 5’+SPM5’+HQDR(w/o Mega) BOE (Buffered Oxide Etch) 23C,Mixture of 40%NH4F and 49%HF SMIC define MB:BOE(10:1), LB:BOE(130:1:7), DB:BOE(200:1) Surfactants are often added to improve wetting Benefit compared to DHF: 1) Low selectivity oxide etch ? for DRAM contact pre-clean 2) Prevent photo resist liftoff ? for KV, Dual gate process For BOE etch with PR on wafers, S/D or Marangoni is used for drying SiO2 / BPSG etching mechanism SiO2 is mainly etched by HF2- SiO2 + 2HF2- + 2H3O+ ? SiF4 + 4H2O SiF4 + 2HF ? H2SiF6 (in HF solution) SiF4 + 2NH4F ? (NH4)2SiF6 (in BOE solution) BPSG is ma
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