集成电路可测性设计之概述.pptVIP

  1. 1、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。。
  2. 2、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  3. 3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
  4. 4、该文档为VIP文档,如果想要下载,成为VIP会员后,下载免费。
  5. 5、成为VIP后,下载本文档将扣除1次下载权益。下载后,不支持退款、换文档。如有疑问请联系我们
  6. 6、成为VIP后,您将拥有八大权益,权益包括:VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
  7. 7、VIP文档为合作方或网友上传,每下载1次, 网站将根据用户上传文档的质量评分、类型等,对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档
查看更多
Fundamentals on Testing and Design for Testability Design Verification, Testing and Diagnosis Design Verification: Ascertain the design perform its specified behavior Testing: Exercise the system and analyze the response to ascertain whether it behaves correctly Diagnosis: To locate the cause of misbehavior after the incorrect behavior is detected Some Real Defects in Chips Processing Faults missing contact windows parasitic transistors oxide breakdown Material Defects bulk defects (cracks, crystal imperfections) surface impurities (ion migration) Time-Dependent Failures dielectric breakdown electromigration Packaging Failures contact degradation seal leaks Faults, Errors and Failures Fault: A physical defect within a circuit or a system May or may not cause a system failure Error: Manifestation of a fault that results in incorrect circuit (system) outputs or states Caused by faults Failure: Deviation of a circuit or system from its specified behavior Fails to do what it should do Caused by an error Fault --- Error --- Failure Scenario for Manufacture Test Purpose of Manufacture Testing Verify Manufacture of Circuit Improve System Reliability Diminish System Cost Cost of repair goes up by an order of magnitude each step away from fab line ASIC What is ASIC: Application Specific Integrated Circuits Why we need ASICs Microelectronic economics Volume Time to market Quality Why Testing is Difficult ? Test application time can be exploded for exhaustive testing of VLSI For a combinational circuit with 50 inputs, we need 250 = 1.126x1015 test patterns. Assume one test per 10-7sec, it takes 1.125x108sec = 3.57yrs. to test such a circuit. Test generation of sequential circuits are even more difficult. Lack of Controllability and Observability of Flip-Flops (Latches) Functional testing may not be able to detect the physical faults How To Do Test Fault Modeling Identify target faults Limit the scope of test generation Make analysis possible Test Generation Au

文档评论(0)

369221 + 关注
实名认证
文档贡献者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档