东南信息学院-poc实验报告.docxVIP

Computer Organization and Architecture COURSE DESIGN A Parallel Output Controller ------ (POC) Southeast university School of Information Science and Engineering Design purpose The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The ISE 14.7 EDA tool is recommended and provided for simulation. Learn about the using of Bi-directional Data Bus (BDB), and use a parallel Bi-directional Data Bus to finish the data transmission between CPU and POC. Introduction and Tasks POC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral Figure 1. System structure diagram As Fig.1 shows the inner connecting of a printer to the system bus through the POC. The com- munication between POC and the printer is controlled by a “handshake” protocol given in Fig.2. Figure 2. The handshake-timing diagram between POC and the printer The handshaking process is described as follows: When the printer is ready to receive a char- acter, it holds RDY=1. The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character at PD and hold RDY at 0 until the character has been printed (e.g. delay 5 or 10ms), then set RDY to 1 again when it is ready to receive the next character. The buffer register BR is used to temporarily hold a character sent from the processor, which char- acter will be transferred to the printer later. The status register SR is used for two control functions: ①SR7 serves as a ready flag to indicate POC is ready or not to receive a new character from the processor. ②SR0 is used to enable the interrupt requests sent by POC. In interrupt mode, If SR0=1, then POC will send an interrupt request signal to processor when it is ready to receive a character (i.e., when SR7=1). If SR0=0,