一个可以综合的Verilog-写的FIFO存储器.docVIP

PAGE 6 - 一个可以综合的Verilog 写的FIFO存储器 Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits. The input/output ports of the FIFO are shown in Figure F-1. Figure F-1. FIFO Input/Output Ports Input ports All ports with a suffix N are low-asserted. Clk— Clock signal RstN— Reset signal Data_In— 32-bit data into the FIFO FInN— Write into FIFO signal FClrN— Clear signal to FIFO