2013spring_11_ch4_2计算机体系结构.pdfVIP

LLec 11 11 How to improve cacheHow to improve cache pperfformance ((cont.)) Cache performance metricsCache performance metrics Miss rateMiss rate – Independent of the speed of hardware. Average memory access time( AMAT) – Better than miss rateBetter than miss rate , butbut – Indirect measure of performance CPUtiCPUtime S CA_2013Spring_Lec11_mem 1.2 EEx1: Impact on mpact on Performanc rformance Suppose a processor executes at – Clock Rate = 200 MHz (5 ns per cycle)Clock Rate = 200 MHz (5 ns per cycle), Ideal (no misses) CPI = 1 Ideal (no misses) CPI = 1.11 – 50% arith/logic, 30% ld/st, 20% control Suppose that 10% of memory operations get 50 cycle miss penalty Suppose that 1% of instructions get same miss penalty Calculate the AMAT and real CPI. •Answer:CPI = ideal CPI + average stalls per instruction = 1.1(cycles//ins) + [ 0.30 (DataMops//ins) x 0.10 (miss/DataMop) x 50 (cycle/miss)] + 1 ((InstMopp/ins)) x 0.01 ((miss/InstMop)p) x 50 ((cyycle/miss)])] = (1.1 + 1.5 + .5) cycle/ins = 3.1 •58% of the time the proc is stalled waiting for memory! •AMATAMAT=(1/1(1/1.3)3)x[[11.11+00.0101x5050]]+(0(0.3/13/1.3)3)x[[11.11+00.11x5050]] • =2.54 S CA_2013Spring_Lec11_mem 1.3 Ex2: Imppact on Performance Assume : Ideal CPI=1 (no misses) L/SL/S’s structures structure . 50% of instructions are data accesses50% of instructions are data accesses Miss penalty is 25 clock cycles Miss rate is 2% How faster would the computer be if all instructions were cache hits? Answer: first compute the performance for always hithits: CPUexecution time =(CPU clock cycles+memory stall cycles)cycles) ××clock cycleclock cycle =(IC ×CPI+0) ×Clock cycle =IC=IC ××11.00 ××clock cyc