Trace Cache计算机体系结构.pptVIP

Trace Cache Bring N instructions per cycle No I-cache misses No prediction miss No packet breaks ! Because branch in each 5 instruction, so cache can only provide a packet in one cycle. What’s Trace ? Trace: dynamic instruction sequence When instructions ( operations ) retire from the pipeline, pack the instruction segments into TRACE, and store them in the TRACE cache, including the branch instructions. Though branch instruction may go a different target, but most times the next operation sequential will just be the same as the last sequential. ( locality ) Whose propose ? Peleg Weiser (1994) in Intel corporation Patel / Patt ( 1996) Rotenberg / J. Smith (1996) Paper: ISCA’98 Trace in CPU Instruction segment Pentium 4: trace cache, 12 instr./per cycle How to do when “Partial Match”? If A prediction correct and B prediction false, it is called “Partial match”. J.Smith: If don’t match, then go to I-Cache Patt: Take A B then go I-cache to get D better get AB rather than none Cost: additional logic to differentiate “How” match Bring ABC but marking C as “inactive” issue When predict miss, then no need to bring C Advantage Trace cache segment are “after” decode. If hit trace cache, then the segment fetched from the trace cache is no need to decoded again. Decode is time-consuming, especially for CISC ISA. Block-Structure Basic idea: Block substitute instruction as atomic unit running in computer. One block is always executed in whole or entirely, but not just half or part of it. Additional mechanism need to solve the exception that happens in the middle of the basic block. If the intermediate result of the basic block is not used by other blocks, then we can use linkage within the block but not the register (that is used by the software) to connect the producer and consumer, which can save space and power. Block-Structure Block is produced by a compiler as trace cache segment. If an exception happens at the middle of the block, then all the bloc