第十二章后端设计.ppt

第十二章 后端设计 Outlines Backend Design Flow Floorplan Place Route Physical Verification Signal Integrity DFM/DFY Steps of Backend/Physical Design Synthesis Floor Planning Placement Scan chain insertion and re-ordering ( optional ) Clock Tree Synthesis Routing Parasitic and netlist extraction Power analysis Signal integrity checking Final timing analysis (STA and simulation) ECO (optional) LVS/DRC Export GDSII LVS/DRC using sign-off tools Backend Flow with ECO Engineering Change Order (ECO) Achieved by adding small amount of cells in limited area, sizing buffers and routing the connections Prevent disturbing the placement and routing of the rest of the chip Keep in mind: Performance, Power, Size, Reliability It is not impossible to develop “plug Play” tools Floorplanning Based on netlist, create areas of functionality on your chip Determine the placement of blocks Determine the placement of I/O pins Determine the power supply strategy Give feedback on how easy your floorplan might be to wire (Global routing) and how big the chip is Chip Floorplanning Considerations Chip level floorplanning High speed block issue Location affect the timing performance Analog block issue clean Vdd/Vss; minimal spacing to digital block; IO location Die size issue Pin limited; Core limited Power-Ground routing issue Power ring width according to power analysis Power strip/mesh spacing Pin placement and IO ring issue (will be talked in next class) Pad pitch vs. bounding rule; ESD; noise isolation; Die Size Issue –cont. Determine the area for standard cells “Utilization” – 70% ? 80%? 90%? Extra space for clk tree synthesis Extra space for scan chain Layers for routing Hard Macro Placement Macros are generally placed around the peripheral I/O ring A contiguous area for standard cells. Higher freedom for your place-and-route tools during placement and routing of the standard cells The goal of macro placement is to: Reduce timing-critical paths between the macros and interfacing log