Michael quirk_半导体制造技术-第19章_硅片测试.pptVIP

Semiconductor Manufacturing TechnologyMichael Quirk Julian Serda ? October 2001 by Prentice HallChapter 19Wafer Test Objectives 1. Discuss the electrical tests done for IC fabrication. 2. Explain the purpose of the in-line parametric test and how it is conducted. 3. Describe the equipment used for in-line parametric tests. 4. State the objectives of the wafer sort test and explain how it is performed. 5. Outline and discuss the different types of wafer sort tests. 6. Discuss test issues associated with wafer sort. 7. State and explain the factors that affect yield at wafer sort. 8. Describe the wafer yield models and discuss yield management. Different Electrical Tests for IC Production(From Design Stage to Packaged IC) Automated Electrical Tester Wafer Fab Process Flow with Test Wafer Test In-line Parametric Test (a.k.a. wafer electrical test, WET) Wafer Sort (a.k.a. wafer probe) The reasons for the in-line parametric test 1. Identify process problems 2. Pass/fail criteria 3. Data collection 4. Special tests 5. Wafer level reliability Location of Wafer Fabrication Electrical Tests Scribe Line Monitor Test Structure Examples of Test Structure Test Structure for First Metal Contacts Sample Suite of In-Line Parametric Tests Sample Suite of In-Line Parametric Tests(continued) Threshold Voltage and Drive Current Data Trends 1. The same die location keeps failing a parameter on a wafer. 2. The same parameter is consistently failing on different wafers. 3. There is excessive variation (e.g., 10%) in measurement data from wafer to wafer. 4. Lot-to-lot failure for the same parameter, indicating a major process problem. Wafer Level Reliability Tests 1. Stressing metal lines for electromigration failure by applying a high current density. 2. Assessing how much charge an oxide layer can hold and for how long before it is destroyed. 3. Determine how much charge can be trapped in an oxide. 4. Evaluate the effect of a new wet cleaning process on oxide growth. In-line