SystemVerilog硬件设计和建模第7-8-9章.pptVIP

* * * * Sections 9.6-9.8 can be referred chapter5 and chapter6 * * * * The only difference is that nested modules is local, not global. pls. give the hierarchy diagram of the example. * * 网表是用线网将端口连接起来的模块实例的列表 verbose: 冗长，啰嗦 * * * * * * * * * * * * * * * * * * * * * * * Variables cannot be aliased. * * * * * do statements while (condition); * do statements while (condition); * do statements while (condition); * * * 在end后面可以跟着一个与对应的begin相同的块名，增加可读性！！！ * * * * * * * * * * * * * * * * 我的确有一个问题：综合后门级不会出现条件选项以外的情况？ * * * 结合前面的例子说明！！！ * * * * * * Draw a picture to show the architecture of module