计算机组成原理 第 6 章.pptVIP

现代计算机组成原理 潘 明 潘 松 编著 第 6 章 16位CISC CPU设计 addrregWr=1; next_state=incPc5; when incPc5 = vma = 1; rw = 0; next_state = incPc6; when incPc6 = vma = 1; rw = 0; if ready = 1 then instrWr = 1; next_state = execute; else next_state = incPc6; end if; when others = next_state = incPc; end case; end process; controlffProc:process(clock, reset) begin if reset = 1 then current_state = reset1 after 1 ns; elsif clockevent and clock = 1 then current_state = next_state after 1 ns; end if; end process; end rtl; 6.2 CPU基本部件设计 6.2.4 寄存器与寄存器阵列 图6-10 寄存器REG的实体结构和RTL图 1．寄存器REG 6.2 CPU基本部件设计 6.2.4 寄存器与寄存器阵列 1．寄存器REG 【例6-6】reg.vhd library IEEE; use IEEE.std_logic_1164.all; use work.cpu_lib.all; entity reg is port( a : in bit16; clk : in std_logic; q : out bit16); end reg; architecture rtl of reg is begin regproc: process begin wait until clk event and clk = 1; q = a after 1 ns; end process; end rtl; 6.2 CPU基本部件设计 2．寄存器阵列RegArray 【例6-7】regarray.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use work.cpu_lib.all; entity regarray is port( data : in bit16; sel : in t_reg; en，clk : in std_logic; q : out bit16); end regarray; architecture rtl of regarray is type t_ram is array (0 to 7) of bit16; signal temp_data : bit16; begin process(clk,sel) variable ramdata : t_ram; begin if clkevent and clk = 1 then ramdata(conv_integer(sel)) := data; end if; temp_data = ramdata(conv_integer(sel)) after 1 ns; end process; process(en, temp_data) begin if en = 1 then q = temp_data after 1 ns; else q =ZZZZZZZZZZZZZZZZ after 1 ns; end if; end process; end rtl; 6.2 CPU基本部件设计 6.2.4 寄存器与寄存器阵列 图6-11 寄存器阵列RegAarray的结构图和RTL图 2．寄存器阵列RegArray 6.2 CPU基本部件设计 6.2.4 寄存器与寄存器阵列 图6-12 寄存器阵列regarray.VHD的仿真波形 2．寄存器阵列RegArray 6.2.5 移位寄存器SHIFT 【例6-8】sheft.VHD library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.cpu_lib.all; entity shift is port ( a : in bit16; sel : in t_shift ; y : out bit16); end shift; architecture rtl of sh