专用集成电路设计中科院段成华.pdfVIP

Assignment 2 1. (7.10) Implement a NAND gate model using the IEEE nine-valued system. For the RS flip-flop shown in Figure 7.60, assume that both —— —— gate outputs are initially U, and that the two inputs R and S are initially 0 and switch to 1 simultaneously. Simulate the circuit at logic gate level when: a. Both gates have identical delays. b. The two gates have different delays. Compare your results. S’