testbanch+Verilog在Modelsim实现3分频及5分频.docVIP

用Verilog语言写的三分频电路 //上升沿触发的分频设计module three(clkin, clkout);input clkin;//定义输入端口output clkout;//定义输出端? reg [1:0] step1, step; always @(posedge clkin)begincase (step)2b00: step=2b01;2b01: step=2b10;2b10: step=2b00;default :step=2b00;endcaseend always @(negedge clkin)begincase (step1)2b00: step1=2b01;2b01: step1=2b10;2b10: step1=2b00;default :step1=2b00;endcaseend assign clkout=~(step[1]|step1[1]);endmodule Testbanch： `timescale1ns/100ps module div3_tb ; wire clkout; reg clkin ; wire [1:0] step1, step; initial begin clkin=0; end always #2 clkin=~clki