《数字电路与系统设计》EDA实验 VHDL设计初步.pptVIP

ARCHITECTURE behave OF statem IS TYPE STATE_TYPE IS (sa, sb, sc,sd); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk,reset) BEGIN IF reset = 1 THEN state = sa; ELSIF clkEVENT AND clk = 1 THEN CASE state IS WHEN sa = IF x=1 THEN state = sb; ELSE state=sa; END IF; WHEN sb = IF x=1 THEN state = sc; ELSE state=sa; END IF; WHEN sc = IF x=1 THEN state=sd; ELSE state=sa; END IF; WHEN sd = IF x=1 THEN state = sd; ELSE state=sa; END IF; END CASE; END IF; --