数字设计基础双语课件（第11章）.pptVIP

11.2 VHDL simulation of dataflow code VHDL simulation uses an infinitesimal time intervalδto keep track of the delays that happen to signals as they are assigned. At time 10+δ, n1 takes its new value, which triggers: sum = cin XOR n1; Time = 10+δ * 11.2 VHDL simulation of dataflow code At time 10+2δ,sum takes its new value. Time = 10+2δ There are no statements with sum on the RHS, so no further statements are triggered. * 11.3 Simulation of structural VHDL The VHDL code for the adder is LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY adder IS PORT ( x, y: IN STD_LOGIC_VECTOR(3 DOWNTO 0); cin: IN STD_LOGIC; sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout: OUT STD_LOGIC); END ENTITY adder; ARCHITECTURE structural OF adder IS SIGNAL carry: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN c0: entity work.fulladd(dataflow) PORT MAP (x(0),y(0),cin,sum(0),carry(1)); * 11.3 Simulation of structural VHDL c1: entity work.fulladd(dataflow) PORT MAP (x(1),y(1),carry(1),sum(1),carry(2)); c2: entity work.fulladd(dataflow) PORT MAP (x(2),y(2),carry(2),sum(2),carry(3)); c3: entity work.fulladd(dataflow) PORT MAP (x(3),y(3),carry(3),sum(3),cout); END ARCHITECTURE structural; Continued During simulation all statements are active at the same time, and will be triggered to execute and re-compute their output values if any of their input signals changes. * 11.4 The uninitialized logic value When a digital electronic device is switched on, all bits stored in flip-flops and memory will initially go to a random value which could be a 1 and could be a 0. This is the value that VHDL refers to as ‘U’. It is important for simulation to verify that these random initialization values do not corrupt the subsequent behavior of the device. Normally, the simulator will initialize all internal signals to ‘U’ instead of 0 and trigger an event on all signals. 1. The uninitialized logic valu