数字设计基础双语课件（第12章）.pptVIP

* * * * * * * * * * * * * * * 12. Describe sequential systems in VHDL 12.1 Defining clocks, flip-flops and registers 12.2 Register Transfer Level (RTL) Coding 12.3 Sequential logic * 12.1 Defining clocks, flip-flops registers 1. Defining a clock signal PROCESS BEGIN clock = ‘0’; WAIT FOR 10 NS; clock = ‘1’ WAIT FOR 10 NS; END PROCESS; There are many ways to define a clock. For example: Simulation waveform * 12.1 Defining clocks, flip-flops registers 2. The D-type flip-flop LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff IS PORT ( d, clock: IN STD_LOGIC; Q: OUT STD_LOGIC); END ENTITY dff; ARCHITECTURE correct OF dff IS BEGIN PROCESS (clock) BEGIN IF ( rising_edge(clock) ) THEN q = d; END IF; END PROCESS; END ARCHITECTURE correct; * 12.1 Defining clocks, flip-flops registers 3. The D-type flip-flop with reset If the Reset is synchronous, then it is ignored until the rising edge of the clock. When the rising edge comes, if Reset=’1’ then q goes to ‘0’. If Reset=’0’, then the flip-flop exhibits normal behavior, i.e. q=d. （1）If the Reset is synchronous * 12.1 Defining clocks, flip-flops registers LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- D-type flip-flop ENTITY dff IS PORT ( d : IN STD_LOGIC; -- Data input clock: IN STD_LOGIC; -- Clock input reset: IN STD_LOGIC; -- Reset input Q : OUT STD_LOGIC); -- Output END ENTITY dff; ENTITY definition * 12.1 Defining clocks, flip-flops registers ARCHITECTURE synch_reset OF dff IS BEGIN PROCESS (clock) BEGIN IF ( rising_edge(clock) ) THEN IF ( reset=’1’ ) THEN q = ‘0’; ELSE q = d; END IF; END IF; END PROCESS; END ARCHITECTURE synch_reset; Architecture declaration * 12.1 Defining clocks, flip-flops registers If the Reset is asynchronous, then it takes immediate effect, no matter what