时序裕量及信号完整性.pptVIP

cadence PCB Knowledge set Improving your process for high-speed PcB design System Timing Closing the loop between timing analysis and signal integrity A PCB Knowledge Set Online Seminar from Cadence Signal Integrity presented by Todd Westerhoff cadence PCB Knowledge set o0 Agenda Basics of system timing analysis Basics of signal integrity analysis Flight time, buffer delay, standard loads and T Key process assumptions Checking and verifying model data Techniques for closing the loop Summary cadence PCB Knowledge set o0 言 Static Timing Analysis Systematic analysis of a synchronous ASIC, PCB or System design, that identifies Logic hazards Clocked timing paths T iming error Required inputs Functional description of circuit(netlist) Component-level timing data Circuit operating (clock) speeds cadence PCB Knowledge set o0 e What is a“ Clocked Timing Path”? A timing path consists of all of the logic between two clocked elements that operate off the same clock signal The timing path is analyzed to ensure that setup and hold requirements are met at the input of each clocked element The slack(delay margin) in the path can be used to derive SI fight time constraints cadence PCB Knowledge set Modern System Design CPU Modern systems are dominated by Combinational logic has been AGP|(→ absorbed into other chips Timing analysis for data buses can be performed using a simplified bus-level timing model cadence PCB Knowledge set o0 Standard Synchronous Data Transfer Drive Flight Time D2 Driving Receiving cadence PCB Knowledge set o0 Flight Time Accounts for the electrical delay of interconnect(PCB etch) between the driving device and recevers Can be estimated for slow speed circuits, must be simulated(signal ntegrity for high speed designs cadence PCB Knowledge set o0 Issues in Synchronous Design Cycle 1 Cycle 2 Clock jitter increases/ decreases the individual clock cycle decreasing the time left for data Driver Clock Skew changes the effective clock period depending on whic