静态时序分析基本原理与时序分析模型.pptVIP

ABRA Quartus@ ll Software Design Series: Timing Analysis Timing analysis basics 92009 Altera Corporatio  Objectives Display a complete understanding of timing analysIs ②2009 Atera Corporaton Altera, Stratix, Arria, Cyclone, MAX Hardcopy Nios, Quartus, and MegaCore are trademarks of Altera Corporation AAOBRA  How does timing verification work? a Every device path in design must be analyzed with respect to timing specifications/requirements Catch timing-related errors faster and easier than gate-level simulation board a Designer must enter timing requirements exceptions Used to guide fitter during placement routing Used to compare against actual results -- OUT CLR ②2009 Atera Corporaton Altera, Stratix, Arria, Cyclone, MAX Hardcopy Nios, Quartus, and MegaCore are trademarks of Altera Corporation AAOBRA  Timing Analysis Basics aunch vs latch edges Setup hold times a Data clock arrival time Data required time Setup hold slack analysis 1O analysis Recovery removal Timing models ②2009 Atera Corporaton a, Stratix, Arria, Cyclone, MAX Hardcopy Nios. Quartus, and Mega core are trademarks of AAOBRA  Path Analysis Types Async Path Data path CLR Clock Paths Async Path Three types of Paths Two types of Analysis Clock Paths clock data paths Data Path 2. Asynchronous* -clock async paths Asynchronous refers to signals feeding the asynchronous control ports of the registers ②2009 Atera Corporaton Altera, Stratix, Arria, Cyclone, MAX Hardcopy Nios, Quartus, and MegaCore are trademarks of Altera Corporation AAOBRA  Launch Latch Edges REG2 CLK Latch Launch Edge Edge CLK DATA Data Valid Launch Edge the edge whichlaunches the data from source register Latch Edge the edge whichlatchesthe data at destination register(with respect to the launch edge, selected by timing analyzer; typically 1 cycle 9 Atera Corporaton Altera, Stratix, Arria, Cyclone, MAX Hardcopy Nios, Quartus, and MegaCore are trademarks of Altera Corporation