计算机组织与结构：版7_04_Cache Memory.pptVIP

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */65 */65 Set Associative Mapping Summary Address length = (s + w) bits Number of addressable units = 2 s+w words or bytes Block size = line size = 2w words or bytes Number of blocks in main memory = 2d Number of lines in set = k Number of sets = v = 2d Number of lines in cache = kv = k * 2d Size of tag = (s – d) bits A set associative cache consists of 64 lines, or slots, divided into two-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses. */65 Set Associative Mapping Summary Address length = (s + w) bits Number of addressable units = 2 s+w words or bytes Block size = line size = 2w words or bytes Number of blocks in main memory = 2d Number of lines in set = k Number of sets = v = 2d Number of lines in cache = kv = k * 2d Size of tag = (s – d) bits A set associative cache consists of 64 lines, or slots, divided into two-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.(7.5.7) */65 */65 Varying Associativity over Cache Size */65 Replacement Algorithms (1)Direct mapping No choice Each block only maps to one line Replace that line */65 Replacement Algorithms (2)Associative Set Associative Hardware implemented algorithm (speed) Least Recently used (LRU) e.g. in 2 way set associative Which of the 2 block is lru? First in first out (FIFO) replace block that has been in cache longest Least frequently used replace block which has had fewest hits Random */65 Write Policy Must not overwrite a cache block unless main memory is up to date (最新式的) Multiple CPUs may have individual caches I/O may address main memory directly */65 Write through All writes go to main memory as well as cache Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date Lots of traffic Slows down writes Remember bogus write through caches! */65 Write back Updates initially made i