计算机组织与结构：14_Superscalar.pptVIP

William Stallings Computer Organization and Architecture8th Edition Chapter 14 Instruction Level Parallelism and Superscalar Processors What is Superscalar? Common instructions (arithmetic, load/store, conditional branch) can be initiated and executed independently Equally applicable to RISC CISC In practice usually RISC independent 独立的,自治的,自主的,单独的,分开的 Why Superscalar? Most operations are on scalar quantities (see RISC notes) Improve these operations to get an overall improvement General Superscalar Organization Superpipelined Many pipeline stages need less than half a clock cycle Double internal clock speed gets two tasks per external clock cycle Superscalar allows parallel fetch execute Superscalar vSuperpipeline Limitations Instruction level parallelism (ILP1) Compiler based optimisation Hardware techniques Limited by True data dependency （真实数据相关性） Procedural dependency （过程相关性） Resource conflicts （资源冲突） Output dependency （输出相关性） Antidependency （反相关性） True Data Dependency （W-R) ADD r1, r2 (r1 := r1+r2;) MOVE r3,r1 (r3 := r1;) Can fetch and decode second instruction in parallel with first Can NOT execute second instruction until first is finished Procedural Dependency Can not execute instructions after a branch in parallel with instructions before a branch Also, if instruction length is not fixed, instructions have to be decoded to find out how many fetches are needed This prevents simultaneous fetches Resource Conflict Two or more instructions requiring access to the same resource at the same time e.g. two arithmetic instructions Can duplicate resources e.g. have two arithmetic units Effect of Dependencies 指出下列程序中存在哪些相关性？ For(i=1;i=100;i=i+1){ Y[i]=X[i]/c; /*S1*/ X[i]=X[i]+c; /*S2*/ Z[i]=Y[i]+c; /*S3*/ Y[i]=c-Y[i]; /*S4*/ Design Issues Instruction level parallelism Instructions in a sequence are independent Execution can be overlapped Governed by data and procedural dependency Machine Parallelism Ability to take advantage of instructi