李广军-ASIC设计-习题答案_Chapter_6_Solutions.pdfVIP

Problems 6.1. Write an interactive testbench for the multiplier of Problem 5.13. Your testbench must be complete with clock and proper timing and multiplier handshaking. Use the following interface for the multiplier, module mult (a, b, start, clk, r, done); input [7:0] a, b; input start, clk; output [15:0] r; output done; . . . endmodule `timescale 1ns/100ps module test_multiplier; reg [7:0] a ; reg [7:0] b ; reg start = 1, clk = 0; wire [15:0] r; wir