李广军-ASIC设计-习题答案_Chapter_4_Solutions.pdfVIP

Problems 4.1. Write a Verilog description for the following function. f (A, B, C, D) = Σ (0, 2, 4, 5, 6, 7, 9, 10, 11), d(1, 13) m `timescale 1ns/100ps module func (input A, B, C, D, output reg y); always @ (A, B, C, D) y = ( ~A B )|(~C D)|(~A ~B ~D)|(A ~B C); endmodule 4.2. Write Verilog code for a 4-to-1 multiplexer with a tri-state output and an active low OutputEnable input. The multiplexer has 4 data inputs (d0, d1, d2, d3) and 2 select inputs (s1, s0). Use case and if statements. `ti