李广军-ASIC设计-习题答案_Chapter_7_Solutions.pdfVIP

Problems 7.1. Generate a switch level description for an AOI gate using NMOS and PMOS transistors (w = (a.b + c.d)’ ). `timescale 1ns/100ps module aoi_3d (input a, b, c, d, output y ); supply0 Gnd; supply1 Vdd; wire im1, im2, im3; pmos #(3,5,7) g1( im1, Vdd, a ), g2( y, im1, b ), g3( im2, Vdd , c ), g4( y, im2, d ); nmos #(2,4,6) g5( y, im3, a ), g6( y, im3, b ), g7( im3, Gnd, c ), g8( im3, Gnd, d );