李广军-ASIC设计-习题答案_Chapter_5_Solutions.pdfVIP

Problems 5.1. Design and implement an SR-latch with active low set and reset inputs. `timescale 1ns/100ps module latch ( input s, r, output q, q_b); nor # (4) g2 ( q, ~r, q_b), g1 ( q_b, ~s, q); endmodule 5.2. Write a negative edge trigger D-Type Flip-flop with an asynchronous active-low reset, a synchronous active-high set, and an active-high clock enable input. `timescale 1ns/100ps module D_ff ( input d, clk, reset, set, en, output reg q, q_b ); always @ ( negedge clk ) begin if (