李广军-ASIC设计-习题答案_Chapter_8_Solutions.pdfVIP

8.1 Design a 2’s complement multiplier using Booth’s algorithm. Your design should consist of two units, a controller and a datapath. The multiplier has an 8-bit A and B inputs and a 16-bit result. module datapath ( input clk, clr_P, load_P, load_B, msb_out, lsb_out, load_A, shift_A, inout [7:0] data ); wire [7:0] ShiftAdd; reg [7:0] A, B, P; reg temp = 1b0; wire co; always @ ( posedge clk ) if (load_B) B = data; always @ ( posedge clk ) if (load_P) P = {ShiftAdd[7], Shif