数字技术 数字技术 2 EDA开发软件与硬件平台.pptx

;1、可编程逻辑器件;1、可编程逻辑器件;1、可编程逻辑器件;1、可编程逻辑器件;1、可编程逻辑器件;1、可编程逻辑器件;1.2.1 基于乘积项技术的PLD;1.2.1 基于乘积项技术的PLD;1.2.1 基于乘积项技术的PLD;1.2.1 基于乘积项技术的PLD;1.2.1 基于乘积项技术的PLD;1.2.1 基于乘积项技术的PLD;1.2.1 基于乘积项技术的PLD;1.2.1 基于乘积项技术的PLD;1.2.2 基于查找表技术的PLD;1.2.2 基于查找表技术的PLD;FLEX10K内部结构;(1) 逻辑阵列LAB是由一系列的相邻LE构成的;(2) 逻辑单元LE结构图;(3) 快速通道(FastTrack) 和I/O单元与专用输入端口;1、可编程逻辑器件;1、可编程逻辑器件;;1、可编程逻辑器件;1、可编程逻辑器件;IP核扩充实例;1、可编程逻辑器件;片上可编程系统实例;1、可编程逻辑器件; PC上使用的PCI-E接口控制器能够提供5GB/s的带宽，通常用于接驳显卡或其它需要高速传输数据的硬件。;1、可编程逻辑器件;上图为使用FPGA实现的视频编码/解码算法的实现示意图;内嵌DSP的FPGA在高速图像处理应用;2、Quartus软件;Quartus II Operating environment;Main Toolbar Modes; 2.1 Quartus II Features;More Features;RTL Viewer;RTL Viewer Uses;Starting RTL Viewer;Optimization;Power Estimation;2.2 Design Methodology;PLD Design Flow;PLD Design Flow;Quartus Design Flow;2.3 Quartus II Projects;Add Design Files Graphic (.BDF, .GDF) AHDL VHDL Verilog EDIF Notes: Files in project directory do not need to be added Add top level file if filename entity name are not the same ;Add User Library Paths User Libraries MegaCore?/AMPP Sm Libraries Pre-Compiled VHDL Packages;Choose EDA Tools Add or Change Settings Later;Auto Device or Choose a Specific Device ;Use Filters for Auto Selection or Picking a Specific Device;Review Results Click on Finish;Assignments Menu;Editing Project Settings;Displays Project Hierarchy after Project Is Analyzed Uses Set Top-Level Entity Make Assignments Locate in Design Files, Floorplan or Chip Editor View Resource Usage Drag Drop Hierarchical Blocks ;Project Navigator – Files Tab;Project Navigator - Design Units Tab;Project Files;Summary;2.4 Design Entry Methods;Text Design Entry;Verilog VHDL;AHDL;HDL Templates;Quartus II Options;Schematic Design Entry;Use the Quick Link or File ? New ? Schematic File;Open the Symbol Window: Use the Toolbar or Double Click Schematic Background;;File ? Create/Update ? Create Symbol…;Block Tool;Megafunctions;MegaWizard Plug-In Manager;MegaWizard Examples ;MegaWizard Output File Selection;EDA Inter