vhdl源代码_计数器.pdfVIP

.专业整理 . 十五计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY fiveteencout IS PORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END fiveteencout; ARCHITECTURE counter OF fiveteencout IS SIGNAL count_int:std_logic_vector(0 to 3); BEGIN PROCESS(clk,reset) BEGIN WAIT UNTIL rising_edge(clk); IF reset = 1 THEN count_int = (OTHERS = 0); ELSIF enable = 1 THEN IF(count_int=1110) THEN count_int=0000; ELSE count_int = count_int 1; --ELSE .学习帮手 .