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976 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, VOL. 11, NO. 6, DECEMBER 2003
High-Throughput LDPC Decoders
Mohammad M. Mansour, Member, IEEE, and Naresh R. Shanbhag, Senior Member, IEEE
Abstract—A high-throughput memory-efficient decoder archi- over LDPC codes allowing them to occupy mainstream ap-
tecture for low-density parity-check (LDPC) codes is proposed plications ranging from wireless applications to fiber-optics
based on a novel turbo decoding algorithm. The architecture communications. Hence, the quest for efficient LDPC decoder
benefits from various optimizations performed at three levels
of abstraction in system design—namely LDPC code design, implementation techniques has become a topic of reasing
decoding algorithm, and decoder architecture. First, the intercon- interest, gradually promoting LDPC codes as serious competi-
nect complexity problem of current decoder implementations is tors to turbo codes on both fronts.
mitigated by designing architecture-aware LDPC codes having The design of LDPC decoder architectures differs from the
embedded structural regularity features that result in a regular decoder design for other classes of codes, in particular turbo
and scalable message-transport network with reduced control
overhead. Second, the memory overhead problem urrent codes, in that it is intimately related to the structure of the code
day decoders is reduced by more than 75% by employing a new itself through its parity-check matrix. The iterative decoding
turbo decoding algorithm for LDPC codes that removes the process of bo odes consists of two
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