数字逻辑设计及应用：chap7 Sequential Logic Design Principles.ppt

Equivalent states pairs: S5—S4 S6—S2 S7—S3 S8—S1 The minimal state/output table Sequence detector design S* AB Z 00 01 11 10 S0 S1 S1 S2 S2 0 S1 S3 S3 S2 S2 0 S2 S1 S1 S4 S4 0 S3 S3 S3 S4 S2 1 S4 S1 S3 S4 S4 1 S The minimal state diagram Sequence detector design Use decomposed assignment, output is Q2; State assignment Sequence detector design Transition list and minimization Transition list and minimization (minimal cost) LA LB LC RA RB RC input：L (turn left)、R (turn right)、H (emergency- flasher）、CLOCK output：six lights (LC,LB,LA,RA,RB,RC) Turn left Turn right Hazard Examples : T-bird tail lights control Step 1: set up enough state with different meaning ; State name state meaning IDLE all lights are off ; L1 one left light is on; L2 two left lights are on; L3 three left lights are on; R1 one rignt light is on; R2 two right lights are on; R3 three right lights are on; LR3 all lights are on ; Examples : T-bird tail lights control Step 2-3: from state diagram to the transition list Examples : T-bird tail lights control Step 4: from the transition list to the transition table Examples : T-bird tail lights control Step 5: get the excite equations for D flip-flop Examples : T-bird tail lights control Output table (Moore machine) Examples : T-bird tail lights control Register design module latch (d,c,q); input d,c; output q; assign q = (c ? d:q); endmodule Always block and Variable … reg[7:0] f ; … always @ (posedge clk) begin variable assignment; end Variable: must be reg , assigned in always block ! Variable: Operational result , must be reg , may be stored in register, assigned in always block. Nonblocking assignment: sequential design f = x y; Blocking assignment: combinational design f = x y; Always block and Variable Register design module