FPGA可编程逻辑器件芯片XC2S150-5CSG144I中文规格书.doc

编号： 时间：2021年x月x日 学海无涯 页码：第 PAGE 3页 共 NUMPAGES 13页 第 第 PAGE 1 页 共 NUMPAGES 1 页 FPGA可编程逻辑器件芯片XC2S150-5CSG144I中文规格书 Spartan-6 FPGA Configuration User Guide UG380 (v2.11) March 22, 2019Chapter4 User Primitives The configuration primitives described in this chapter are provided for users to access FPGA configuration resources during or after FPGA configuration. For additional information and instantiation templates, refer to UG615, Spartan-6 Libraries Guide for HDL Designs. BSCAN_SPARTAN6 JTAG is a standard four-pin interface: TCK, TMS, TDI, and TDO. Many applications are built around this interface. The JTAG TAP controller is a dedicated state machine inside the configuration logic. BSCAN_SPARTAN6 provides access between the JTAG TAP controller and user logic in fabric. There are up to four instances of BSCAN_SPARTAN6 for each device. Each instance of this design element can handle one JTAG USER instruction (USER1 through USER4) as set with the JTAG_CHAIN attribute. To handle all four USER instructions, four of these elements can be instantiated, and the JTAG_CHAIN attribute must be set appropriately. Table4-1 lists the BSCAN_SPARTAN6 port descriptions. Table 4-1:BSCAN_SPARTAN6 Port Descriptions Signal Name Type Function SEL Output Active-High interface selection output. SEL=1 when the JTAG instruction register holds the corresponding (USER1, USER2, USER3, or USER4) instruction. Change in Update_IR state. SEL changes on the falling edge of TCK in the UPDATE_IR state of the TAP controller. RESET Output Active-High reset output. RESET=1 during the TEST-LOGIC-RESET state, PROGRAM_B, or during power-up. This signal is deasserted on the falling edge of TCK. TDI Output Fed through directly from the FPGA TDI pin. DRCK Output DRCK is the same as TCK in the Capture_DR and Shift_DR states. If the interface is not selected by the instruction register, DRCK remains High. CAPTURE Output Active-High pulse indicating t