FPGA可编程逻辑器件芯片XC2S150-4FG456C中文规格书.docVIP

编号： 时间：2021年x月x日 学海无涯 页码：第 PAGE 3页 共 NUMPAGES 13页 第 第 PAGE 1 页 共 NUMPAGES 1 页 FPGA可编程逻辑器件芯片XC2S150-4FG456C中文规格书 RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009Chapter1 Introduction to the RocketIO GTX Transceiver Overview The RocketIO? GTX transceiver is a power-efficient transceiver for Virtex-5 FPGAs. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications: ?Current Mode Logic (CML) serial drivers/buffers with configurable termination, voltage swing, and coupling. ?Programmable TX pre-emphasis, RX equalization, and linear and decision feedback equalization (DFE) for optimized signal integrity. ?Line rates from 750Mb/s to 6.5Gb/s, with optional 5x digital oversampling required for rates between 150Mb/s and 750Mb/s. The nominal operation range of the shared PMA PLL is from 1.5GHz to 3.25GHz. These are nominal values, see DS202: Virtex-5 FPGA Data Sheet for specifications. ?Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channel bonding, and clock correction. ?Fixed latency modes for minimized, deterministic datapath latency. ?Beacon signaling for PCI Express designs and Out-of-Band signaling including COM signal support for SATA designs. ?RX/TX Gearbox provides header insertion and extraction support for 64B/66B and 64B/67B (Interlaken) protocols. ?Receiver eye scan: ?Vertical eye scan in the voltage domain for testing purposes ?Horizontal eye scan in the time domain for testing purposes The first-time user is recommended to read High-Speed Serial I/O Made Simple[Ref1], which discusses high-speed serial transceiver technology and its applications. Table1-1 lists some of the standard protocols designers can implement using the GTX transceiver. The Xilinx CORE Generator? tool includes a Wizard to automatically configure GTX