FPGA可编程逻辑器件芯片XC2S150-5FGG456C中文规格书.docVIP

编号： 时间：2021年x月x日 学海无涯 页码：第 PAGE 3页 共 NUMPAGES 13页 第 第 PAGE 1 页 共 NUMPAGES 1 页 FPGA可编程逻辑器件芯片XC2S150-5FGG456C中文规格书 RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009Chapter 6:GTX Transmitter (TX) TX PRBS Generator Overview Pseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of high-speed links. These sequences appear random but have specific properties that can be used to measure the quality of a link. The GTX PRBS block can generate several industry-standard PRBS patterns. Table 6-13 lists the available PRBS patterns and their typical uses. Ports and Attributes Table 6-14 defines the TX PRBS generator ports. There are no attributes in this section. Description Each GTX transceiver includes a built-in PRBS generator. This feature can be used in conjunction with other test features, such as loopback and the built-in PRBS checker, to run tests on a given channel. To use the PRBS generator, the PRBS test mode is selected using the TXENPRBSTST port. Table 6-14 lists the available settings. Table 6-13: Pseudo-Random Bit Sequences Name Polynomial Length of Sequence (bits)Consecutive Zeros Typical Use PRBS-7 1+X 6+X 7 (inverted)27–17Used to test channels with 8B/10B.PRBS-231+X 18+X 23 (inverted) 223–123ITU-T Recommendation O.150, Section 5.6. One of the recommended test patterns in the SONET specification.PRBS-311+X 28+X 31 (inverted)231–131 ITU-T Recommendation O.150, Section 5.8. A recommended PRBS test pattern for 10 Gigabit Ethernet. See IEEE 802.3ae-2002.Table 6-14:TX PRBS Generator Ports Port Direction Clock Domain Description TXENPRBSTST0[1:0] TXENPRBSTST1[1:0]In TXUSRCLK2Transmitter test pattern generation control. A pseudo-random bit sequence (PRBS) is generated by enabling the test pattern generation circuit. 00: Test pattern generation off (standard operation mode)01: Enable 27–1 PRBS generation 10: Enable 223–1 PRBS generation 11: Enable 231–1 PRBS ge