FPGA可编程逻辑器件芯片XC2S150-5FGG256C中文规格书.docVIP

编号： 时间：2021年x月x日 学海无涯 页码：第 PAGE 3页 共 NUMPAGES 13页 第 第 PAGE 1 页 共 NUMPAGES 1 页 FPGA可编程逻辑器件芯片XC2S150-5FGG256C中文规格书 Virtex-5 FPGA Configuration Guide UG191 (v3.13) July 28, 2020Chapter4 User Primitives The following configuration primitives are provided for users to access FPGA configuration resources during or after FPGA configuration. BSCAN_VIRTEX5 JTAG is a standard four-pin interface: TCK, TMS, TDI, and TDO. Many applications are built around this interface. The JTAG TAP controller is a dedicated state machine inside the configuration logic. BSCAN_VIRTEX5 provides access between the JTAG TAP controller and user logic in fabric. There are up to four instances of BSCAN_VIRTEX5 for each device, each instance is controlled with the JTAG_CHAIN parameter. Table4-1 lists the BSCAN_VIRTEX5 fabric pins. Table 4-1:BSCAN_VIRTEX5 Pin Table Pin Name Type Description SEL Output Active-High interface selection output. SEL=1 when the JTAG instruction register holds the corresponding USER1-4 instruction. Change in Update_IR state. SEL changes on the falling edge of TCK in the UPDATE_IR state of the TAP controller. RESET Output Active-High reset output. RESET=1 during the TEST-LOGIC- RESET state, PROGRAM_B, or during power up. This signal is deasserted on the falling edge of TCK. TDI Output Fed through directly from the FPGA TDI pin. DRCK Output DRCK is the same as TCK in the Capture_DR and Shift_DR states. If the interface is not selected by the instruction register, DRCK remains High. CAPTURE Output Active-High pulse indicating the Capture_DR state. This signal is asserted on the falling edge of TCK. UPDATE Output Active-High pulse indicating the Update_DR state. This signal is asserted on the falling edge of TCK. SHIFT Output Active-High pulse indicating the Shift_DR state. This signal is asserted on the falling edge of TCK. TDO Input TDO input driven from the user fabric logic. This signal is internally sam