FPGA可编程逻辑器件芯片XC2S150-5FGG456I中文规格书.docVIP

编号： 时间：2021年x月x日 学海无涯 页码：第 PAGE 3页 共 NUMPAGES 13页 第 第 PAGE 1 页 共 NUMPAGES 1 页 FPGA可编程逻辑器件芯片XC2S150-5FGG456I中文规格书 RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009 Chapter 7 GTX Receiver (RX) This chapter shows how to configure and use each of the functional blocks inside the GTX receiver. Receiver Overview Each GTX transceiver includes an independent receiver, made up of a PCS and a PMA. Figure 7-1 shows the functional blocks of the receiver (RX). High-speed serial data flows from traces on the board into the PMA of the RX, into the PCS, and finally into the FPGA logic. Refer to Appendix E, “Low Latency Design,” for latency information on this block diagram. The key elements within the GTX receiver are:1.“RX Termination and Equalization,” page 1622.“Decision Feedback Equalization,” page 1663.“RX OOB/Beacon Signaling,” page 1734.“RX Clock Data Recovery,” page 1795.“Serial In to Parallel Out,” page 1836.“Oversampling,” page 1857.“RX Polarity Control,” page 1898.“PRBS Detection,” page 190 9. “Configurable Comma Alignment and Detection,” page 191 Figure 7-1:GTX RX Block Diagram RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009 Decision Feedback Equalization Figure 7-4 illustrates a conceptual view of the DFE. The DFE allows better compensation of transmission channel losses by providing a closer adjustment of filter parameters than when using a linear equalizer. However, a DFE cannot remove the pre-cursor of a transmitted bit. A linear equalizer allows pre-cursor and post-cursor attenuation, but has only a coarse adaptor to the transmission channel characteristic. The GTX_DUAL DFE in the GTX RX is a time-discrete adaptive high-pass filter (1). The TAP values of the DFE are the coefficients of this filter that are set by the automatic TAP value controller. The optimization criteria for the TAP values and the DFECLK delay is the vertical eye opening. The DFE_CFG_(0/1) attribute switches off auto-calib