FPGA可编程逻辑器件芯片XC2S150-6CS144C中文规格书.docVIP

编号： 时间：2021年x月x日 学海无涯 页码：第 PAGE 3页 共 NUMPAGES 13页 第 第 PAGE 1 页 共 NUMPAGES 1 页 FPGA可编程逻辑器件芯片XC2S150-6CS144C中文规格书 RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009Power Control when PLLPOWERDOWN is asserted, only the shared PMA PLL and all clocks derived from it are stopped. Recovery from this power state is indicated by the assertion of the PLLLKDET signal on the tile whose REFCLKPWRDNB signal is asserted . TX and RX Power Down When the TX and RX power-down signals are used in non PCI Express implementations, TXPOWERDOWN and RXPOWERDOWN can be used independently. However, when these interfaces are used in non PCI Express applications, only two power states are supported, as shown in Table 5-13. When using this power-down mechanism, the following must be True: ? TXPOWERDOWN[1] and TXPOWERDOWN[0] are connected together.? RXPOWERDOWN[1] and RXPOWERDOWN[0] are connected together.? TXDETECTRX must be strapped Low.?TXELECIDLE must be strapped to TXPOWERDOWN[1] and TXPOWERDOWN[0]. Power Control Features for PCI Express Operation The GTX_DUAL tile implements all of the functions needed for power control states compatible with those defined in the PCI Express and PIPE specifications. When implementing PCI Express compatible power control, the following conditions must be met: ? The TXPOWERDOWN and RXPOWERDOWN signals on each GTX transceiver must be connected together to ensure that they are in the same state at all times.? The REFCLKPWRDNB and PLLPOWERDOWN signals must be held in inactive states.Table 5-13:TX and RX Power States for Non PCI Express Operation TXPOWERDOWN[1:0] or RXPOWERDOWN[1:0]Description 00P0 mode. Transceiver TX or RX is active sending or receiving data. 11 P2 mode. Transceiver TX or RX is idle.Table 5-14:TX and RX Power States for PCI Express Operation TXPOWERDOWN[1:0] and RXPOWERDOWN[1:0]TXDETECTRX TXELECIDLE Description 00 (P0 state)00The PHY is transmitting data. The MAC provides data byte