FPGA可编程逻辑器件芯片XC2S150-6FGG256I中文规格书.docVIP

编号： 时间：2021年x月x日 学海无涯 页码：第 PAGE 3页 共 NUMPAGES 13页 第 第 PAGE 1 页 共 NUMPAGES 1 页 FPGA可编程逻辑器件芯片XC2S150-6FGG256I中文规格书 Spartan-6 FPGA Configuration User Guide UG380 (v2.11) March 22, 2019Master BPI Configuration Interface Determining the Maximum Configuration Clock Frequency In Master BPI mode, the FPGA delivers the configuration clock. The master configuration clock frequency of the FPGA is set through the BitGen -g ConfigRate option. The BitGen -g ConfigRate option sets the nominal configuration clock frequency. The default BitGen ConfigRate setting of 2 is recommended. This default value sets the nominal master CCLK frequency to 2MHz, which satisfies timing requirements for the leading BPI flash families. If the timing requirements discussed in this section are satisfied, the BitGen ConfigRate setting can be increased for a faster configuration time. When determining a valid ConfigRate setting, these timing parameters must be considered:? FPGA nominal master CCLK frequency (BitGen ConfigRate)? FPGA Master CCLK frequency tolerance (FMCCKTOL)? A[25:0] outputs valid after CCLK falling edge (TBPICCO)? BPI flash address to output valid (access) time (TACC)?FPGA data setup time to CCLK rising edge (TBPIDCC) The master configuration clock of the FPGA has a tolerance of FMCCKTOL. Due to the master configuration clock tolerance (FMCCKTOL), the BitGen -g ConfigRate option must be checked so that half the period for the worst-case (fastest) master CCLK frequency is greater than the sum of the FPGA address valid time, BPI flash access time, and FPGA set up time, as shown in Equation 2-1. Equation 2-1Power-On Sequence Precautions At power-on, the FPGA automatically starts its configuration procedure. When the FPGA is in a Master-BPI configuration mode, the FPGA asserts FCS_B Low and drives a sequence of addresses to read the bitstream from a parallel NOR flash. The parallel NOR flash must be ready for asynchronous reads before the FPGA drives FCS_B