微机课件沈润杰2015年微机原理课件lec09_hardware.pptxVIP

Microcomputer Principle and Interfacing Techniques微机原理与接口技术 ;2015/10/28;Digital design fundamentalswith 8086/8088 Microprocessor;2015/10/28;2015/10/28;8086/88 Pinout;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;2015/10/28;8086/8088 based minimum system;Typical Architecture;The 8066/8088 Microprocessors;Device Specifications;The pin-outs;8086 CPU;Pin-out Definitions;Pin-out Definitions;Pin-out Definitions;Pin-out Definitions;Pin-out Definitions;Basic functions: Clock generation. RESET synchronization. READY synchronization. Peripheral clock signal. Connection of the 8284 and the 8086.;8284A Clock Generator;Clock generation: Crystal is connected to X1 and X2. XTAL OSC generates square wave signal at crystal’s frequency which feeds: An inverting buffer (output OSC) which is used to drive the EFI input of other 8284As. 2-to-1 MUX F/C selects XTAL or EFI external input. The MUX drives a divide-by-3 counter (15MHz to 5MHz). This drives: The READY flipflop (READY synchronization). A second divide-by-2 counter (2.5MHz clk for peripheral components). The RESET flipflop. CLK which drives the 8086 CLK input.;RESET: Negative edge-triggered flipflop applies the RESET signal to the 8086 on the falling edge. The 8086 samples the RESET pin on the rising edge.;Bus Buffering and Latching;Bus Buffering and Latching;BUS Buffering and Latching;BUS Timing;Bus Timing;Bus Timing;Bus Timing;During T1: The address is placed on the Address/Data bus. Control signals M/IO, ALE and DT/R specify memory or I/O, latch the address onto the address bus and set the direction of data transfer on data bus. During T2: 8086 issues the RD or WR signal, DEN, and, for a write, the data. DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads. During T3: Th