cadence版图设计自动布局布线synthesis, place route.ppt

Synthesis, Place Route Ketan Joshi Director of Marketing, SPR Design Concept to Implementation Design Implementation Plan Productive Design Plan with Cadence SPR Productive Design Plan with Cadence SPR Productive Design Plan with Cadence SPR Ambit BuildGates Quick Reference Card What is it? A logic synthesis tool Like conventional synthesis, with greater performance and capacity Who is the Typical User? Logic designers using ASIC or COT flows Why is it Better? Higher performance/capacity Superior QoR Integrated Static Timing sign-off Integrated Chip Synthesis and STA Ambit BuildGates: Comprehensive Synthesis Verilog, VHDL, EDIF Integrated, Sign-off timing engine Time Budgeting Graphical UI Distributed synthesis AmbitWare Test Synthesis TCL - user interface SDF,GCF, PDEF Sun, HP, IBM Business StatisticsConventional Synthesis Over 500 customers More than 3000 active licenses worldwide Leading ASIC vendor support AMI, Atmel, Chip Express, Faraday Technology, Fujitsu, IBM, Kawasaki Steel, LSI, Lucent, Matsushita, Mitsubishi, NEC, OKI, Toshiba, VLSI Productive Design Plan with Cadence SPR Low Power Synthesis OptionQuick Reference Card What is it? An option to Ambit BuildGates and PKS Enables less power consuming design Who is the Typical User? Logic designers using ASIC or COT flows; Battery powered applications, consumer electronics Why is it Better? Integrated, single tool solution Superior power savings Faster runtime Low Power Synthesis Option RTL and gate level optimizations Auto clock gating Sleep-mode for modules, components Fully design-constraint driven Accurate -- RTL transformations based on gate level timing/power Power analysis Integrated transparently Customer Benchmark Data Significant power savings over conventional flows Customer 1: 48% power reduction Customer 2: 58% power reduction Better timing, area, and power numbers than competitors Customer 2: 8.3% better power; 5.6% smaller area; better slack