文本文稿数电新建2 lec23.pptVIP

Prepared by Jin Digital Logic Design and ApplicationJin YanhuaLecture #23 Clocked Synchronous State-Machine Analysis Clocked Synchronous State-Machine Design Sequential Logic Circuit Feedback sequential circuits No explicit flip-flops; state stored in feedback loops Clocked synchronous sequential circuits —— Finite State Machines (FSM) Use edge-triggered flip-flops All flip-flops are triggered from the same master clock signal, and therefore all state change together asynchronous sequential circuits State-machine structure (Mealy) State-machine structure (Moore) State-machine stru