SynplicityTimingClosure90nmFPGADevelopments-可编程逻辑器件开发.pdf

Developments in Physical Synthesis to Developments in Physical Synthesis to solve Timing Closure in 90nm FPGAs solve Timing Closure in 90nm FPGAs Gael Paul, Synplicity inc. Copyright © 2005 Synplicity, Inc. Agenda Agenda The Timing Closure Problem Traditional delay models break down Simultaneous Synthesis and Placement Is it enough for FPGAs? Graph-Based Physical Synthesis When wires matters most Optional Design Planning for Advanced Users Design Analysis Timing Islands Copyright © 2005 Synplicity, Inc. Interconnect Delay Matters Interconnect Delay Matters % of Path Delay 100% Interconnect Delay 80% 50% How to accurately model How to accurately model interconnect delay? interconnect delay? 20% Cell Delay 0.25µ 0.18µ 0.13µ 0.09µ Process Technology Node Copyright © 2005 Synplicity, Inc. Statistical Estimation (circa 1999) Statistical Estimation (circa 1999) 0.0ns 0.34ns Driver Load Wire Load Model 1 0.34 Assumed 2 0.34 local route 3 0.34 0.0ns 2.56ns 4 0.34 5 0.65 Driver