Verilog实现的8位超前进位加法器.docVIP

Verilog实现的8位超前进位加法器。 经过modelsim验证正确可用，在DC下综合成功 //文件名：add_8.v //模块名：add_8 // `timescale 1ns/1ns module add_8 ( input [7:0]a, input [7:0]b, input cin, output [7:0] s, output co ); wire [7:0]c_tmp; wire [7:0]g; wire [7:0]p; assign co = c_tmp[7]; assign g[0] = a[0] b[0], g[1] = a[1] b[1], g[2] = a[2] b[2], g[3] = a[3] b[3], g[4] = a[4] b[4], g[5] = a[5] b[5], g[6] = a[6] b[6], g[7] = a[7] b[7]; assign p[0] = a[0] | b[0], p[1] = a[1] | b[1], p[2] = a[2] | b[2], p[3] = a[3] | b[3], p[4] = a[4] | b[4], p[5] = a[5] | b[5], p[6] = a[6] | b[6], p[7] = a[7] | b[7