基于VHDL的电子时钟设计(附代码和仿真波形).pptVIP

电子时钟设计;设计要求;系统组成 ;系统组成方框图 ;1. 10进制可预置计数器模块;2. 6进制可预置计数器模块;24进制可预置计数器模块;4. 译码显示模块;电子时钟设计与仿真 ;10进制计数器VHDL程序;begin dout = count; process(clk,reset,din) begin if reset=0then count = din ; c=0; elsif rising_edge(clk) then if count = 1001 then count = 0000; c=1; else count = count+1; c=0; end if; end if; end process; end Behavioral; ;10进制计数器??真;6进制计数器VHDL程序 ;process(clk,reset,din) begin if reset= 0 then count = din; c=0; elsif rising_edge(clk) then if count=101 then count=000; c=1; else count=count+1; c=0; end if; end if; end process; dout = count; end Behavioral; ;6进制计数器仿真 ;24进制计数器VHDL程序;process(clk,reset,din) begin if reset= 0 then count = din; elsif rising_edge(clk) then if count(3 downto 0)=1001 then count(3 downto 0)=0000; count(5 downto 4)=count(5 downto 4) +1; else count(3 downto 0)=count(3 downto 0)+1; end if; if count=100011 then count=000000; end if; end if; end process; dout = count; end Behavioral; ;24进制计数器仿真 ;译码器VHDL程序;process(din) begin case din is when 0000 = dout=0000001;--0 when 0001 = dout=1001111;--1 when 0010 = dout=0010010;--2 when 0011 = dout=0000110;--3 when 0100 = dout=1001100; --4 when 0101 = dout=0100100;--5 when 0110 = dout=0100000;--6 when 0111 = dout=0001111;--7 when 1000 = dout=0000000;--8 when 1001 = dout=0000100;--9 when others = dout=1111111; end case; end process; end Behavioral; ;顶层设计VHDL程序; hourl: out std_logic_vector(6 downto 0); --小时低位输出 hourh: out std_logic_vector(6 downto 0)); --小时高位输出 end clock; architecture Behavioral of clock is component counter10 is Port ( clk : in std_logic; reset : in std_logic; din : in std_logic_vector(3 downto 0); dout : out std_logic_vector(3 downto 0); c:out std_logic); end component; component counter6 is Port ( clk : in std_logic; reset : in std_logic; din : in std_l